1. Field of the invention
The present invention relates to an emulation system, and more specifically to an emulation system used for debugging a software stored in a single-chip microcomputer and the like.
2. Description of related art
Recently, a wide variety of application instruments incorporating a single-chip microcomputer therein have been reduced into practice. With this tendency, a wide variety of single-chip microcomputers to be incorporated into the application instruments have been developed and manufactured on a mass production basis. In this connection, it is a general practice that, prior to development of a single-chip microcomputer, an emulation system is developed for the purpose of verifying an operation of a software used in the single-chip microcomputer to be developed and an operation of the application instrument.
In a single-chip microcomputer to be incorporated into an application instrument, it is an ordinary practice to develop a product which has a central processing unit (CPU) in common to other ones and a peripheral device different from other ones. Accordingly, in order to emulate a target product, an emulation system is constituted of a CPU emulator for carrying out emulation of the common CPU, and a peripheral emulator for carrying out emulation of the peripheral device. Therefore, for each different application instrument, the emulation is carried out by changing only the peripheral emulator. Thus, a single-chip microcomputer which can be used for a wide variety of application instruments, can be emulated.
However, for a wide variety of application instruments, it is not so effective to develop one peripheral emulator for each one product. Therefore, one approach has been often used to provide an emulation circuit internally in a single-chip microcomputer to be incorporated in the application instruments, and to control it by a signal supplied from an external, so as to cause it to function as a peripheral emulator. In this case, ten and a few external terminals are required to transfer interface signals between the CPU emulator and the peripheral emulator, and therefore, it actually becomes impossible to conduct the emulation operation while using these external terminals as an input/output port.
In order to overcome this problem, it has been proposed to use a plurality of peripheral emulators in combination so that, a function which cannot be emulated because of mutual transfer of interface signals, is compensated for by another peripheral emulator. This example is shown by Japanese Patent Application Laid-open Publication No. JP-A-02-130640.
In addition, for a product having a function added to a conventional peripheral circuit, it becomes in some cases that a first peripheral emulator provided for an existing peripheral circuit cannot emulate a peripheral circuit having an additional function. In the case of emulating the peripheral circuit having the additional function, by means of a second peripheral emulator separately added, it is in some cases an indispensable condition that an interrupt control function must be emulated by a single peripheral emulator, dependently upon the nature of the interrupt function. Therefore, if an interrupt request is generated in the inside of the second peripheral emulator which does not execute the emulation of the interrupt control function, the emulation is executed by supplying an interrupt request signal through an external terminal to the first peripheral emulator which executes the emulation of the interrupt control function. This example is shown by Japanese Patent Application Laid-open Publication No. JP-A-05-334460.
In this proposal, however, in the case of emulating the peripheral circuit having the additional function by the second peripheral emulator, since the interrupt request signal generated in the second peripheral emulator is supplied through the external terminal to the first peripheral emulator, a priority order and a vector code for the interrupt request signal in question have been previously determined as a matter of course. As a result, the priority order and the vector code for the interrupt request signal generated in the second peripheral emulator are different in an interrupt request processing timing between the emulation system and the actual single-chip microcomputer. Accordingly, in the case of emulating the product having the function added to the conventional peripheral circuit, it is not possible to easily execute the emulation without changing the interrupt priority order and by adding only the additional peripheral emulator.
Referring to FIG. 1, there is shown a block diagram of the first prior art example of the conventional emulation system.
The shown emulation system includes a CPU emulator 1, peripheral emulators 2 and 3 and a target system 4. The CPU emulator 1 and the peripheral emulators 2 and 3 are coupled to each other through an emulation bus 5. The CPU emulator 1 can access through the emulation bus 5 to a peripheral device internally provided in each of the peripheral emulators 2 and 3. Therefore, the peripheral device internally provided in each of the peripheral emulators 2 and 3 is operated exclusively to each other, by action of the access from the CPU emulator 1. In other words, when a certain peripheral device is emulated, the peripheral function of only one of the peripheral emulators 2 and 3 is accessed.
The CPU emulator 1 has external terminals 6A, 6B, 6C and 6D. The peripheral emulator 2 has external terminals 7A, 7B, 7C, 7D, 7E and 7F. The peripheral emulator 3 has external terminals 8B, 8C, 8D, 8E and 8F. In addition to the emulation bus 5, signal lines 9 and 10 are connected between the CPU emulator 1 and the peripheral emulator 2, and a signal line 36 is connected between the peripheral emulator 2 and the peripheral emulator 3. A signal line 12 is connected between the CPU emulator 1 and the target system 4, and a signal line 37 is connected between the target system 4 and the peripheral emulator 2. Signal lines 13 and 14 are connected between the target system 4 and the peripheral emulator 3.
Referring to FIG. 2, there is shown a block diagram of the two peripheral emulators 2 and 3 provided in the emulator system shown in FIG. 1.
As shown in FIG. 2, the peripheral emulator 2 includes a CPU 16, a port circuit 17, an interrupt control circuit 18 and a peripheral circuit 19, which are coupled to an internal bus 20. The external terminals 7A and 7B are connected to the interrupt control circuit 18, and the external terminal 7C is coupled to the internal bus 20. The external terminal 7D is connected to the CPU 16, the interrupt control circuit 18 and the peripheral circuit 19, and the external terminal 7F is connected to the port circuit 17. The external terminal 7F is connected to the interrupt control circuit 18.
The external terminal 7D is supplied with an emulation signal 21 for designating whether the peripheral emulator 2 is operated as the single-chip microcomputer or the peripheral emulator. If the emulation signal 21 of a logical "1" level is supplied to the external terminal 7D from the CPU emulator 1, the peripheral emulator 2 is put in a condition of operating as the peripheral emulator. In this condition, the CPU 16 is put into a disabled condition, and on the other hand, the interrupt control circuit 18, the peripheral 19 and the port circuit 17 are put in a condition allowing to be accessed from the CPU emulator 1 through the emulation bus 5 and the external terminal 7C. The port circuit 17 receives and outputs an input/output signal through the external terminal 7E from and to the target system 4, and information is transferred between the port circuit 17 and the internal bus 20. The interrupt control circuit 18 receives an interrupt request signal 15 from the peripheral circuit 19, and interrupt control signals are interfaced through the external terminals 7A and 7B between the CPU emulator 1 and the interrupt control circuit 18.
Thus, in the case of emulating the peripheral circuit 19 internally provided in the peripheral circuit 2, the CPU emulator 1 accesses the peripheral circuit 19 through the emulation bus 5 and the internal bus 20, and input/output signals are transferred between the peripheral circuit 19 and the target system 4 through the internal bus 20 and the external terminal 7E.
When an interrupt is generated internally in the peripheral circuit 19, the interrupt request signal 15 of a logical "1" level is outputted to the interrupt control circuit 18, which in turn discriminates whether or not the generation of the interrupt request signal 15 is permitted, and also discriminates the priority order of the generated interrupt request signal 15. If the generation of the interrupt request signal 15 is permitted, the interrupt control circuit 18 generates the vector code corresponding to the generated interrupt request signal 15, and the generated vector code is supplied through the emulation bus 5 to the CPU emulator 1. In response to this, a processing being executed in the CPU emulator 1 is interrupted, and an interrupt request corresponding to the interrupt request signal 15 from the peripheral circuit 19 is acknowledged, so that the interrupt processing is executed.
On the other hand, the peripheral emulator 3 includes a CPU 22, a port circuit 23, an interrupt control circuit 24, a peripheral circuit 27, and an AND circuit 38, which are connected as shown. The CPU 22, the port circuit 23, the interrupt control circuit 24, and the peripheral circuit 27 are coupled to an internal bus 34. The external terminal 8B is coupled to the internal bus 34. The external terminal 8D is connected to the CPU 22, the interrupt control circuit 24 and the peripheral circuit 27, and the external terminals 8E and 8C are connected to the port circuit 23. The external terminal 8F is connected to an output of the AND circuit 38, which in turn has a pair of inputs connected to the interrupt control circuit 24 and the peripheral circuit 27, respectively.
Similarly to the peripheral emulator 2, the external terminal 8D of the peripheral emulator 3 is supplied with the emulation signal 35 for designating whether the peripheral emulator 3 is operated as the single-chip microcomputer or the peripheral emulator. If the emulation signal 35 of a logical "1" level is supplied to the external terminal 8D from the CPU emulator 1, the peripheral emulator 3 is put in a condition of operating as the peripheral emulator. In this condition, the CPU 22 is put into a disabled condition, and on the other hand, the interrupt control circuit 24, the peripheral circuit 27 and the port circuit 23 are put in a condition allowing to be accessed from the CPU emulator 1 through the emulation bus S and the external terminal 8B. The port circuit 23 receives and outputs input/output signals through the external terminals 8C and 8E from and to the target system 4, and information is transferred between the port circuit 23 and the internal bus 20.
If an interrupt request signal 39 is generated in the peripheral circuit 27, the interrupt request signal 39 is transferred through the AND circuit 38 to the external terminal 8F, and furthermore, is supplied through the signal line 36 and the external terminal 7F to the interrupt control circuit 18 of the peripheral emulator 2. In the interrupt control circuit 18 of the peripheral emulator 2, the interrupt request signal 39 supplied from the peripheral emulator 3 is discriminated as an interrupt request signal having the interrupt priority order and the vector code of the external terminal 7F, similarly to the interrupt requested generated in the inside of the peripheral emulator 2, and then, a corresponding interrupt processing is conducted. Thus, the peripheral emulator 3 carries out the emulation of an peripheral circuit which is not internally provided in the peripheral emulator 2 or the peripheral circuit having a priority order different from that of the peripheral circuit 19 internally provided in the peripheral emulator 2.
Next, explanation will be made on an emulation of a peripheral circuit having an added function. FIG. 3 is a block diagram of a second prior art example of the conventional emulation system using a peripheral circuit internally provided in the peripheral emulator 2. In FIG. 3, elements similar to those shown in FIG. 1 are given the same Reference Numerals.
As shown in FIG. 3, this emulation system includes the CPU emulator 1, the peripheral emulators 2 and 3, the target system 4, and an additional circuit 40. Since the emulation of the peripheral device in this second prior art example is the same as that of the first prior art example shown in FIG. 1, explanation thereof will be omitted. Explanation will be focused on an emulation operation of the added function using the additional circuit 40 for multiplexing the input/output signals of the conventional peripheral circuit, as an additional function to the conventional peripheral circuit.
In the system shown in FIG. 3, since the peripheral circuit 19 internally provided in the peripheral emulator 2 does not comply with an emulation of the additional function, an emulation function is realized by the CPU emulator 1, the peripheral emulators 2 and 3, the target system 4, the emulation bus 5 and the additional circuit 40 corresponding to the additional function. The peripheral emulators 2 and 3 are provided with external terminals 7E and 7G and 8G and 8H, respectively, as external terminals for control signals for the additional circuit 40. These external terminals 7E and 7G and 8G and 8H are connected to the additional circuit 40 through signal lines 41, 42, 43 and 44, respectively.
As mentioned above, in order to execute the emulation by using the peripheral circuit 19 internally provided in the peripheral emulator 2, since the peripheral circuit 19 itself does not comply with the emulation of the additional function, it is necessary to provide the additional circuit 40. However, in order to transfer the signals for controlling the additional circuit 40, at least four external terminals are required, and therefore, it is practically impossible to execute the emulation while using these external terminals as the input/output port.
Under this circumstance, in the case of executing the emulation of the peripheral circuit having the added function, by use of the peripheral emulator 3, the interrupt request signal 39 generated in the peripheral circuit 27 internally provided in the peripheral emulator 3 is supplied through the external terminal 8F to the interrupt control circuit 18 of the peripheral emulator 2, similarly to the prior art example shown in FIG. 1. However, the interrupt priority order and the vector code of the conventional peripheral circuit are different from the interrupt priority order and the vector code of the peripheral circuit having the added function. This means that the timing of the interrupt processing in the emulation is different from the timing of the interrupt processing in an actual single-chip microcomputer.
As mentioned above, since one set of the interrupt priority order and the vector code are generated for each one interrupt request signal, it is impossible to execute the emulation of the peripheral circuit having the function added to the conventional peripheral circuit, without changing the priority order of the interrupt for the purpose of maintaining succession of a user's software. Therefore, it is impossible to emulate the peripheral circuit having the added function, by only addition of the peripheral emulator.